This is because the original implementation was most likely optimized to fit the most functionality possible in the smallest space possible. It's very likely that many observed phenomena has a common cause, i.e they are artifacts of what strategy was used to implement the intended behaviour of the original circuit.Kweepa wrote:Really? I'd be interested to know why. If anything I would have thought that simulating the observable behaviour would be better, since you could take shortcuts that work with FPGA.tlr wrote:To fit it in a reasonable amount of space (like the CPLD mentioned) you need to know enough to deduce most of the actual silicon implementation, not just the observable behaviour.
If we try to implement what we can observe from our tests, observation for observation, the implementation will be a big mess of special cases.
If we try to deduce the actual original implementation, chances are that phenomena present in the original design that we haven't observed, will actually be present in our implementation as well.
The latter was occasionally the case when we implemented x64sc over x64.