vic-1110 8k ram cart upgrade (and other solutions)

[lordbubsy]

Thank you people for this very valuable thread!
Especially thanks to eslapion!

I have a "naked" VIC-1210 3K RAM Cartridge PCB.
I ordered an SRAM chip 32K x 8 and a few 74HCT08.
With the info here I'll try to make a working 35k RAM expansion.
It's exciting to experiment with those digital circuits and it would be very satisfying in case it actually works!

Is there a way to disable the VIC-1210 3K RAM part?
Perhaps to disconnect RAM1, RAM2 and RAM3?

[Mike]

- it has dynamic ram instead of static

It would be interesting to know if the DRAM refresh introduces wait cycles.

The program MG Raster employs a cycle exact interrupt to change the VIC registers several times on each line, and during the visible part of the screen it relies upon that there are 71 (NTSC: 65) memory cycles available on each raster. If there are some wait cycles introduced by the DRAM refresh, the splits will 'drift' to the right. Here's how it's supposed to look.

Could you conduct a test with this program, maybe with a screenshot?

Edit: Nevermind. Actually, the RAM expansion wouldn't even have a way to actually stop the CPU. The refresh cycles (just) need to happen when the CPU doesn't access the RAM, but that's easily possible while VIC does its fetches - and VIC anyway cannot access what's at the cartridge expander ... so there.

Is there a way to disable the VIC-1210 3K RAM part?
Perhaps to disconnect RAM1, RAM2 and RAM3?

The best solution would be a threefold alteration switch. The three common contacts go to the CS of each chip pair responsible for one K, the three 'ON' contacts go to the corresponding /RAMx edge connectors, and the three 'OFF' contacts should be tied high to +5 V, preferably over a pull-up resistor.

With the VFLI mod, the extra resistor network inside the VIC-20 already does this job, it disables any external +3K expansion (and ensures the VIC/CPU bus separation also works correctly).

[pallas]

I was thinking the same: is my ram expansion slower?
Here is the screenshot:

[Mike]

I was thinking the same: is my ram expansion slower? Here is the screenshot: [...]

... which confirms my later edit. Your DRAM expander does not introduce wait states for the CPU.

[pallas]

So I have a vic-20 (with dynamic ram) which is faster than a c64 because the c64 has dynamic ram

[Mike]

So I have a vic-20 (with dynamic ram) which is faster than a c64 because the c64 has dynamic ram.

Erm, no.

On the C64, the VIC-II is responsible for DRAM refresh. For this it does 5 refresh cycles on each raster line, during horizontal retrace.

What slows down the CPU a bit, is the extra DMA necessary for the VIC-II to fetch text screen data in the first raster of each text line (the so-called badlines). Enabled sprites also steal CPU cycles. For more info, please refer to the timing schemes at AAY64.

At last, the PAL C64 only runs at 0.985 MHz, while the PAL VIC-20 is clocked at 1.10 MHz, but both NTSC C64 and VIC-20 run at 1.03 MHz.

[lordbubsy]

The best solution would be a threefold alteration switch. The three common contacts go to the CS of each chip pair responsible for one K, the three 'ON' contacts go to the corresponding /RAMx edge connectors, and the three 'OFF' contacts should be tied high to +5 V, preferably over a pull-up resistor.

I've found a schematic of a 35k expansion which confirms that.
http://www.baltissen.org/images/mem-exp.gif

With the VFLI mod, the extra resistor network inside the VIC-20 already does this job, it disables any external +3K expansion (and ensures the VIC/CPU bus separation also works correctly).

I've got to pick that up again. I removed all RAM except the color RAM of course. And replaced it with the 6264. I didn't put the resister network in place, but it already works. And before I replace the color ram for the bigger version, I really need to read all those threads again.

[Mike]

I didn't put the resistor network in place, but it already works.

Without the resistor network, only the inputs of UD9 remain to define the signal level of the original /RAMx lines on the mainboard. UD9 itself regards these open lines as having H-level (but only barely), for this reason the VIC-20 on its own works as expected with the extra 3K.

Trouble starts when a cartridge is added, which also uses the /RAMx signals. The signal level put on the /RAMx lines by the open inputs of UD9 is ~2.4 V, for another TTL input this is also H-level (at the lowest permitted voltage though), but for a CMOS input this is definitely undefined. Actually, it will put that part of the CMOS logic into a state where both transistors to +5V and GND conduct, leading to overly increased power consumption of the chip. Furthermore the external expansion might put its data on the bus seemingly at random, leading to bus contention and crashes.

[lordbubsy]

Trouble starts when a cartridge is added

I see, I have a Final Expansion 3, and I have added the resisters on the upper side of the main board at the IC socket. So that should be safe. Though I have to order some components before I can test on that board.

The VIC-20 expansion port has address OUTPUT lines. In this specific case, only A0 to A12 are used. 13 address lines creates a logical space of 8192 units.

The LS08 is used to create A13 and A14 which the HY62256A requires. It does so by ANDing signals BLK1, BLK2, BLK3 and BLK5. Also, the Chip Select line of your ram chip is triggered by access to any of the above BLK areas which requires a cascaded ANDing.

There are 4 logic gates in a 74LS08 and they are connected as follows:

Gate 1: BLK1 AND BLK3 to A14
Gate 2: BLK1 AND BLK2 to A13 (also sent to Gate 4)
Gate 3: BLK3 AND BLK5 to Gate 4
Gate 4: A13 AND (output of Gate 3) to Chip Select

This allows the VIC which is normally designed to address memory in areas of 8k to use a single 32k SRAM chip.

1) So /BLK1 AND /BLK3 generates A14 and /BLK1 AND /BLK2 generates A13?

2) In another schematic I saw /RAM1 AND /RAM2 AND /RAM3 AND /BLK1 generating A14.
http://www.baltissen.org/images/mem-exp.gif

3) Yet in another schematic /BLK2 NAND /BLK3 generates A14.
http://commodore.hcc.nl/forum/9/146344?p=269944#p269344

I'm confused, I do understand that /BLK1 /BLK2 /BLK3 /BLK5 /RAM1 /RAM2 /RAM3 are the chip select signals for additional RAM or ROM chips. But I fail to see how combining them results in A13 and A14.

Is it just reading the schematic of the VIC-20 and common digital knowledge to recover this mystery?
Is there any hardware book for the VIC-20 where it all is explained?


Besides putting a 32k RAM chip on a VIC-1210 3K RAM Cartridge I am thinking of piggybacking a 6264 8k RAM chip for block 5 and a 62256 32k RAM chip for block 0 to 3 upon the BASIC ROM which I already substituted for an EPROM. http://www.baltissen.org/images/mem-exp.gif
That looks like a very elegant way for adding a 35k Expansion.

[Mike]

Indeed there are different ways to combine /BLK1, /BLK2, /BLK3 and /BLK5 to form A13, A14 and /CS.

The only prerequisite is, that one of the /BLKx going low results in a unique one of the four possible combinations of A13, A14; and if any one of the /BLKx signals goes low, so should also do /CS. Take this table:

Code: Select all

/BLK1 /BLK2 /BLK3 /BLK5   A13  A14  /CS
  1     1     1     1      x    x    1
  0     1     1     1      0    0    0
  1     0     1     1      0    1    0
  1     1     0     1      1    0    0
  1     1     1     0      1    1    0

(x: don't care)

... which results in:

Code: Select all

A13 := /BLK1 AND /BLK2
A14 := /BLK1 AND /BLK3
/CS := /BLK1 AND /BLK2 AND /BLK3 AND /BLK5 = A13 AND (/BLK3 AND /BLK5)

The function of the 32K RAM expansion still remains the same even when the /BLKx signals or A13/A14 are permuted. Finally, CA0 to CA12 on the expansion connector span the complete 8K range for each of the blocks and can directly be connected to A0 to A12 of the RAM chip.

http://www.baltissen.org/images/mem-exp.gif

In this schematic, CA13 is directly connected to the 62256. That fails to provide four different combinations of A13 and A14 for the four blocks, regardless what logic is there for A14, as CA13=1 for BLK1, BLK3 and BLK5.

[lordbubsy]

Thank you for the explanation.
I think I understand most of what you're saying.
What I don't understand is how you get this true table?

Code: Select all

1 /BLK1 /BLK2 /BLK3 /BLK5   A13  A14  /CS
2   1     1     1     1      x    x    1
3   0     1     1     1      0    0    0
4   1     0     1     1      0    1    0
5   1     1     0     1      1    0    0
6   1     1     1     0      1    1    0
7
8 (x: don't care)

Let's assume block 3 is activated, so /BLK3 = "0" which is true for line 5.
That’s the address space from $6000-$7FFF where A13 and A14 are "1".
What am I missing here?
Could you elaborate how to set up that true table?

[eslapion]

2) In another schematic I saw /RAM1 AND /RAM2 AND /RAM3 AND /BLK1 generating A14.
http://www.baltissen.org/images/mem-exp.gif

FALSE!

/RAMx covers the 3k expansion area so it couldn't possibly cover A14 as these signals cover a 1024 bytes (10 adress lines required) area.

The plan you gave requires both a 8k x 8 SRAM as well as a 32k x 8 SRAM to generate a 35k expansion.

All /RAMx access request are forwarded to the 8k x 8 RAM chip and all accesses to /BLKx are forwarded to the 32k x 8 RAM chip.

Added edit:
Correction!
This plan uses the 32k x 8 chip for BLK 1,2 and 3 as well as the 3k RAM expansion then puts BLK5 in the separate 8k x 8 chip and only IT can be toggled to read-only mode.

This is probably for compatibility with self modifying code cartridges but as demonstrated with the game Crazy Antics, you MUST place in read-only mode ALL the RAM for full compatibility with dumped cartridges.

Also, it uses pin 18 CR/W for !WE which is not buffered. This also doesn't work. The proper pin to use is pin 17 VR/W.

So AFAIK, as it is, this plan doesn't work.

[lordbubsy]

Well, to be honest, those other two schematics were google finds, and it was my way trying to understand and eventually build a VIC-20's RAM expansion.
But I've not found any schematics of the VIC-1210 3K, VIC-1110 8K or the VIC-1111 16K expansion. Do they exist on the internet?

However, I'm definitely most interested in building your 32k expansion on my VIC-1210 3K pcb.
According to your information in your post I made a schematic of it.

The VIC-20 expansion port has address OUTPUT lines. In this specific case, only A0 to A12 are used. 13 address lines creates a logical space of 8192 units.

The LS08 is used to create A13 and A14 which the HY62256A requires. It does so by ANDing signals BLK1, BLK2, BLK3 and BLK5. Also, the Chip Select line of your ram chip is triggered by access to any of the above BLK areas which requires a cascaded ANDing.

There are 4 logic gates in a 74LS08 and they are connected as follows:

Gate 1: BLK1 AND BLK3 to A14
Gate 2: BLK1 AND BLK2 to A13 (also sent to Gate 4)
Gate 3: BLK3 AND BLK5 to Gate 4
Gate 4: A13 AND (output of Gate 3) to Chip Select

This allows the VIC which is normally designed to address memory in areas of 8k to use a single 32k SRAM chip.

Did I interpreted it correctly?
edit:
Schematic corrected! Changed 18(CR/W) to 17(VR/W)
edit2:
Added a 10k pullup resistor at the switch.

Furthermore I'm trying to comprehend the concept of generating A13 and A14 out of BLK1-3, which Mike has given me some insight already.

[Mike]

Furthermore I'm trying to comprehend the concept of generating A13 and A14 out of BLK1-3, which Mike has given me some insight already.

You need to differentiate between the address range of the 6502 and the address range of the RAM chip.

CA0 .. CA13 are the lower 14 bits of the CPU Address-Bus exposed at the expansion port. Of these bits, only CA0 .. CA12 are used. They span the full 8K range of all the blocks, and are directly connected to A0 .. A12 of the 62256 RAM chip.

The 74LS08 then "translates" the /BLKx select signals into logical addresses which are only relevant to the RAM chip. At the RAM chip, its A13 and A14 pins "select" between the four available 8K regions. So what happens is:

Code: Select all

 CPU Address:    Block:   RAM Chip "Address"

$2000 .. $3FFF    BLK1      $0000 .. $1FFF    (A14=0, A13=0)
$4000 .. $5FFF    BLK2      $4000 .. $5FFF    (A14=1, A13=0)
$6000 .. $7FFF    BLK3      $2000 .. $3FFF    (A14=0, A13=1)
$A000 .. $BFFF    BLK5      $6000 .. $7FFF    (A14=1, A13=1)

... and accesses outside the blocks named above simply deselect the RAM chip.

It does not matter that in this example the logical addresses at the RAM chip are "swapped" between BLK2 and BLK3, as long as all addresses are unique and map to the whole range.

According to [Eslapions] information in [his] post I made a schematic of [the RAM expansion]. [...] Did I interpret it correctly?

For the most part it's correct, but, as Eslapion already wrote, you need to connect the R/W pin of the RAM chip to VR/W on the expansion port. CR/W does not work.

[lordbubsy]

You need to differentiate between the address range of the 6502 and the address range of the RAM chip.

That was the key, now it's perfectly clear to me. Thanks a lot!

For the most part it's correct, but, as Eslapion already wrote, you need to connect the R/W pin of the RAM chip to VR/W on the expansion port. CR/W does not work.

Ok, that confirms the connections on my VIC-1210 where R/W also is connected to VR/W.

I got the info from:
http://www.zimmers.net/anonftp/pub/cbm/ ... /32kB.html
perhaps there is an error…

I'll change the schematic above for correctness.