Re: VIC-2000 Expander. Modern Power Using Retro Parts!
Posted: Wed Oct 25, 2017 5:40 pm
I considered the S-VID mod since my LCD also has that input, but it violates one of my rules... VIC-20 must remain stock.
I did some testing with an overlay tonight, and think that it may not be possible using the port supplied 1.022727 PH2 clock.
Here is why...
The main system clock is 14.318178 MHz, which is divided by the 6560 like this...
A) Divide by 4 = Color Burst @ 3.579545 MHz
B) Divide by 14 = 6502 Clock @ 1.022727 MHz
I was thinking that I could simply divide PH2 by 64 to lock to a line, but that math is slightly off.
1022727 / 64 = 15980.109375, which yields a 15.980 KHz line frequency.
Unfortunately, the 6560 generates a line frequency of 15.625 KHz.
What would happen is a slight shift to the right along all vertical edges of overlayed graphics.
I cannot think of a way to multiply PH2 by 14 using only 1980's logic components, which would have worked perfectly.
With an FPGA, it would be one line of Verilog, but I ain't doin' this the easy way!
I might get away with sampling the horizontal sync and reset the 6 bit counter on each line, but this might still be visible as a series of serrated edges, much like what you see when you say "POKE 36864,130" to put the VIC into interlace mode.
I may try this divide by 64 and lock to hsync idea anyhow.
It won't be much effort to throw an AVR, 512K of SAM and a few counters on a board to draw a bitmap over the VIC screen.
If it does work with acceptable shift, then I may continue with an overlay design.
If not, back to the VIC-20 dual display.
Brad
I did some testing with an overlay tonight, and think that it may not be possible using the port supplied 1.022727 PH2 clock.
Here is why...
The main system clock is 14.318178 MHz, which is divided by the 6560 like this...
A) Divide by 4 = Color Burst @ 3.579545 MHz
B) Divide by 14 = 6502 Clock @ 1.022727 MHz
I was thinking that I could simply divide PH2 by 64 to lock to a line, but that math is slightly off.
1022727 / 64 = 15980.109375, which yields a 15.980 KHz line frequency.
Unfortunately, the 6560 generates a line frequency of 15.625 KHz.
What would happen is a slight shift to the right along all vertical edges of overlayed graphics.
I cannot think of a way to multiply PH2 by 14 using only 1980's logic components, which would have worked perfectly.
With an FPGA, it would be one line of Verilog, but I ain't doin' this the easy way!
I might get away with sampling the horizontal sync and reset the 6 bit counter on each line, but this might still be visible as a series of serrated edges, much like what you see when you say "POKE 36864,130" to put the VIC into interlace mode.
I may try this divide by 64 and lock to hsync idea anyhow.
It won't be much effort to throw an AVR, 512K of SAM and a few counters on a board to draw a bitmap over the VIC screen.
If it does work with acceptable shift, then I may continue with an overlay design.
If not, back to the VIC-20 dual display.
Brad