6561 Die Shot Reversing Explorations
Posted: Sun Oct 22, 2017 5:28 pm
I thought I might start a new topic to continue the 6561 die shot reversing that I began last year. Recently I started looking at this again, and rather than continuing from where I got to last time, I have decided to look at a different part of the chip, this time the Y decoder. The Y decoder is in the part of the chip highlighted below:
The Y decoder is responsible for generating various signals in response to the current value of the vertical counter (the counter is in the area below the highlighted area). The Y decoder has as part of its input 10-bits from the vertical counter, the bottom bit of which is, as far as I can tell, ignored by the Y decoder (and it also isn't stored in the read-only raster line control registers). The Y decoder also has the interlace bit as input, but we'll come on to that in a later post.
This evening I will start with looking at the generation of the vertical blanking signal. In a subsequent post we'll look at the other vertical signals and then the horizontal signals. It's a bit later in the evening than I intended, so I'm going to cut straight to the logic diagram and will fill in the details of how I arrived at this diagram in my next post.
Here it is:
For those that were following my posts last year, this decoder is very similar to what we saw with the colour decoder. This diagram was built in logisim. On the left hand side we have a logisim counter that represents the 10-bit vertical counter. Also on the left is the value of the interlace bit. I've included this because its there, even though it doesn't affect vertical blanking.
So what we have is the 10 bits from the vertical counter, and the inverse of each of these 10 bits, and then the interlace bit and its inverse, all entering the Y decoder on the left. So 22 inputs in total coming in on the left hand side. At the top of the diagram, we have two pull ups. Logisim provides a pull up resistor that functions in the way that the depletion mode transistor pull up in the 6561 functions, so I chose this to model that pull up. Within the Y decoder we've got transistors at various points that pull down to ground. The placement of these transistors is what determines where blanking starts and where it stops. One of the vertical lines controls where it starts and the other where it stops. You'll then notice that the bottom of these two lines connects to an SR latch flip flop. What happens is that one of those vertical lines turns the flip flop output on and the other will turn it off. The output of this flip flop is the vertical blanking signal. The flip flop holds the vertical blanking signal on until the vertical counter reaches the line that it should turn off.
From simulating this, I can tell you that vertical blanking is on from a counter value of 2 up to and including a counter value of 19. Please note that this would be line 1 to 9 (inclusive) in the value that is stored in the raster line control register. I've clocked it round a few times and every time the first two lines are still off and its only when it gets to line 2 (or line 1 in the raster control register) does it turn on vertical blanking. I've also double checked the point at which it turns off and this is at line 20 (or line 10 as we would see in in the raster control register).
In the next post I'll show the silicon and explain how I arrived at the diagram.
The Y decoder is responsible for generating various signals in response to the current value of the vertical counter (the counter is in the area below the highlighted area). The Y decoder has as part of its input 10-bits from the vertical counter, the bottom bit of which is, as far as I can tell, ignored by the Y decoder (and it also isn't stored in the read-only raster line control registers). The Y decoder also has the interlace bit as input, but we'll come on to that in a later post.
This evening I will start with looking at the generation of the vertical blanking signal. In a subsequent post we'll look at the other vertical signals and then the horizontal signals. It's a bit later in the evening than I intended, so I'm going to cut straight to the logic diagram and will fill in the details of how I arrived at this diagram in my next post.
Here it is:
For those that were following my posts last year, this decoder is very similar to what we saw with the colour decoder. This diagram was built in logisim. On the left hand side we have a logisim counter that represents the 10-bit vertical counter. Also on the left is the value of the interlace bit. I've included this because its there, even though it doesn't affect vertical blanking.
So what we have is the 10 bits from the vertical counter, and the inverse of each of these 10 bits, and then the interlace bit and its inverse, all entering the Y decoder on the left. So 22 inputs in total coming in on the left hand side. At the top of the diagram, we have two pull ups. Logisim provides a pull up resistor that functions in the way that the depletion mode transistor pull up in the 6561 functions, so I chose this to model that pull up. Within the Y decoder we've got transistors at various points that pull down to ground. The placement of these transistors is what determines where blanking starts and where it stops. One of the vertical lines controls where it starts and the other where it stops. You'll then notice that the bottom of these two lines connects to an SR latch flip flop. What happens is that one of those vertical lines turns the flip flop output on and the other will turn it off. The output of this flip flop is the vertical blanking signal. The flip flop holds the vertical blanking signal on until the vertical counter reaches the line that it should turn off.
From simulating this, I can tell you that vertical blanking is on from a counter value of 2 up to and including a counter value of 19. Please note that this would be line 1 to 9 (inclusive) in the value that is stored in the raster line control register. I've clocked it round a few times and every time the first two lines are still off and its only when it gets to line 2 (or line 1 in the raster control register) does it turn on vertical blanking. I've also double checked the point at which it turns off and this is at line 20 (or line 10 as we would see in in the raster control register).
In the next post I'll show the silicon and explain how I arrived at the diagram.