My hardware project :: GCart 2011
Posted: Wed Aug 10, 2011 5:20 pm
Hi,
During my introduction (http://sleepingelephant.com/ipw-web/bul ... &start=315) I mention my newfound interrest in the VIC-20 together with my son, and ideas on a hardware project.
Don't really know where this will land but feedback is always welcome.
Anyway it has been changed a bit, still overkill gargantua, but.
# 64k - 1024k SRAM. No Flash. With the usual banking, write protect, individual enable/disable. All banks including 3k.
# 8k Kernal, Diskmanagement, Basic extensions with fullscreen editor.
# A specific block can be mapped during NMI assertion. This is used to call up the main menu and monitor ... among other things.
# Up to 32GB SD managed by a co-processor. It will load data as fast as the VIC can receive them. D64 support and ordinary files. TAP support would be cool perhaps? Little of on how to handle the UI with this mix though.
# Audio decoder for MIDI, MP3, FLAC, WAV, OGG, etc. Can play directly from disk ... which is probably the only viable option anyway.
# RTC with battery backup.
# WiFi. FTP to the SD card. NTP client (which nearly defeats the purpose of backed up RTC). Kernel will understand URI sort off. As in ...
LOAD "http://www.zimmers.net/anonftp/pub/cbm/ ... a.prg",8,1
RESET
# Also ... if there will be room in the CPLD a really good hardware random generator.
# 3 Buttons (RESET, NMI, DISK).
# 0.96" OLED Display for text, icons etc.
So far the hardware for a prototype is almost finnished.
Xilinx CPLD, Audio Codec VS1053b, PIC24, WiFi from Microchip.
4 layer board.
Regarding Software the kernel is half there. Most MP3 and SD for the PIC stuff is recycled, and most of the BASIC and Diskmanager will be recycled from really old code I wrote in the 80's.
During my introduction (http://sleepingelephant.com/ipw-web/bul ... &start=315) I mention my newfound interrest in the VIC-20 together with my son, and ideas on a hardware project.
Don't really know where this will land but feedback is always welcome.
Anyway it has been changed a bit, still overkill gargantua, but.
# 64k - 1024k SRAM. No Flash. With the usual banking, write protect, individual enable/disable. All banks including 3k.
# 8k Kernal, Diskmanagement, Basic extensions with fullscreen editor.
# A specific block can be mapped during NMI assertion. This is used to call up the main menu and monitor ... among other things.
# Up to 32GB SD managed by a co-processor. It will load data as fast as the VIC can receive them. D64 support and ordinary files. TAP support would be cool perhaps? Little of on how to handle the UI with this mix though.
# Audio decoder for MIDI, MP3, FLAC, WAV, OGG, etc. Can play directly from disk ... which is probably the only viable option anyway.
# RTC with battery backup.
# WiFi. FTP to the SD card. NTP client (which nearly defeats the purpose of backed up RTC). Kernel will understand URI sort off. As in ...
LOAD "http://www.zimmers.net/anonftp/pub/cbm/ ... a.prg",8,1
RESET
# Also ... if there will be room in the CPLD a really good hardware random generator.
# 3 Buttons (RESET, NMI, DISK).
# 0.96" OLED Display for text, icons etc.
So far the hardware for a prototype is almost finnished.
Xilinx CPLD, Audio Codec VS1053b, PIC24, WiFi from Microchip.
4 layer board.
Regarding Software the kernel is half there. Most MP3 and SD for the PIC stuff is recycled, and most of the BASIC and Diskmanager will be recycled from really old code I wrote in the 80's.