In another thread, Mike wrote:The VIC chip is not able to access *anything* at the expansion port. There's a timing barrier in-between, formed by three 74245 buffer chips. They're necessary, because the 6502 cannot tri-state its address bus.
In yet another thread, Vic20-Ian wrote:Ref earlier comments ref tristate:
While you are hacking the hardware, could the tristate buffers be removed by replacing 6502 with the Atari 6502 or the 6510?
"Tri-stating the buses
The 6510 and an Atari version of the 6502 can be tri-stated. 573s have an OC input that takes care of that. The 6510 and the Atari version go into tri-state mode the moment AEC/BE becomes (L). A 573 is active the moment OC is (L). This means an inverter is needed: IC07d.
The R/W has to be tri-stated as well: IC11c, a 125 buffer, takes care of this.
ID signal I123 takes care of enabling IC05, the 573 that outputs the data. IC06c, an OR gate, makes sure that IC05 is tri-stated as well during a tri-state demand from the outside world.
Supporting the 6510
The major difference with the 6502 is the 6-bits onboard I/O port. An added 6526 takes care of that. The 6526 may only be visible at the addresses $0000 and $0001. Two 688s, IC08 and IC09 take care of that. Signal I121 and OR gate IC06a take care of the fact whether the 6526 will be enabled at all or not.
When reading from $0000 or $0001, we must make sure that there is no conflict with IC04, the 573 that reads the data from the outside world. Inverter IC07c and OR gate IC06b take care of that."
http://www.baltissen.org/newhtm/ttl6502.htm
and
Vic20-Ian also wrote:"On the original 400/800 design, a series of tri-state buffers surround the 6502 and
do the job of 'detaching' the 6502.
To lower the chip count on the XL & XE lines, Atari developed a custom version of the 6502 which had the simple
tri-state buffers built-in."
If I understand the article correctly it may be that an Atari XL or XE has a Tristate capable 1.7MHz 6502.
Could this be dropped into the Vic and then remove the tri-state buffers to overcome your problem?
http://www.atarimax.com/freenet/freenet ... cle.php?38
Let's keep the discussion in the thread where it really belongs.
The 6502, together with the three 74245 buffers and a few other ICs in the select logic perform a function, which actually could be perceived similar to the capability of the 6510 to tri-state its address bus, so another bus master can address the memory.
However, all the additional hacks necessary to put a 6510 in place of the 6502 in the VIC-20 would presumably result in something quite resembling another well known computer, only it would be using VIA instead of CIAs (and at another address), would 'lack' the SID, and of course keep the VIC-I.
Anyway, what's the point in hacking around the mainboard, just so external memory could be read by VIC-I, if there's a straightforward solution? Namely, putting 8K RAM in place where it can be accessed by the VIC, instead of the 'original' 5K RAM, thus lifting a restriction on the mainboard which has been put into the design just by accident.
Actually, in the meantime I came up with an even simpler solution than what I described here 3 and a half years ago: it replaces the four 6116 2Kx8 SRAM chips with a single 6264 8Kx8 SRAM, and dispenses with UC4 and U13 alltogether - they are not anymore needed! That's the alternate solution, that RichardC64 also discussed with me over PM.
In the end it all boils down whether there is any interest by other people to keep the discussion up. If there's no live discussion, people shouldn't wonder when improvements ultimately are kept under the rug.
