Denial

Hmm. So I have 2 AT28C256 (32K ROM) with A14 tied to GND. I loaded both my image and the Choplifter image onto each ROM. When I try a PEEK(40960) I would have hoped to have seen either $0F or $09. Unfortunately I'm seeing $FF.

I have:
/BLK5 signal connected to /CE on the ROM. /CE is also connected to 5V through a 1K pull-up resistor.
CR/W going into an inverter (74HC04) with the output going into /OE on the ROM

On my PCB I've done a similar thing for BLK1 and BLK2 and I'm able to see the 19967 bytes free startup screen and I can write and read from the 2 8K RAM chips I have in those sockets. Just in case I had a fan-out problem with the /OE signal, I've tried removing both RAM chips in BLK1 & BLK2.

On occasion I have noticed that the RAM doesn't always get seen at startup too. I wonder if the 1K pull-up resistors are the problem?

Gonna take a break from this for now. I might try removing the pull-ups later and see what happens.

SparkyNZ wrote:So I have 2 AT28C256 (32K ROM) with A14 tied to GND.

What is the EPROM's A13 connected to? If you used CA13 on the expansion port, that's wrong. BLK5 only covers 8 KB, and only the address lines CA0 to CA12 are necessary to address the whole contents of BLK5.

CA13 happens to be 1 within BLK5, and your cartridge hardware then addresses $2000..$3FFF within the EPROM address range - which likely is not what you wanted. A13 of the EPROM should be tied to GND as well, and that arrangement in turn has of course to be disconnected from CA13 in the VIC-20.

I have:
/BLK5 signal connected to /CE on the ROM. /CE is also connected to 5V through a 1K pull-up resistor.
CR/W going into an inverter (74HC04) with the output going into /OE on the ROM

There's absolutely no need to load /BLK5 with an extra pull-up! The involved LS138 actively drives /BLK5 to both logic levels.

As for the /OE input of the EPROM, the 74HC04 is of the wrong logic family for the job. You'd want to use either LS or HCT. On its own, the timing of CR/W also is incorrect for the intended purpose - silencing the output drivers of the EPROM in case it's errorneously written to. In MINIMON, I use /OE = /(CR/W & SΦ2) with one NAND gate of a 74LS00.

Mike wrote: ↑Sat Apr 05, 2025 2:35 am What is the EPROM's A13 connected to? If you used CA13 on the expansion port, that's wrong. BLK5 only covers 8 KB, and only the address lines CA0 to CA12 are necessary to address the whole contents of BLK5.

CA13 happens to be 1 within BLK5, and your cartridge hardware then addresses $2000..$3FFF within the EPROM address range - which likely is not what you wanted. A13 of the EPROM should be tied to GND as well, and that arrangement in turn has of course to be disconnected from CA13 in the VIC-20.

Yup. I have CA13 connected to A13. I'll ground that and remove those pullups. I may have a 74LS04 floating around if I'm lucky. Thanks for the tips - will try in the daytime

SparkyNZ wrote:I may have a 74LS04 floating around if I'm lucky.

You really should use a 74LS00 and do /OE = /(CR/W & SΦ2) - as I already wrote, CR/W on its own has the wrong timing.

Mike wrote: ↑Sat Apr 05, 2025 6:47 am

SparkyNZ wrote:I may have a 74LS04 floating around if I'm lucky.

You really should use a 74LS00 and do /OE = /(CR/W & SΦ2) - as I already wrote, CR/W on its own has the wrong timing.

Thankfully I do have some old 74LS00 chips. I haven't had time to fiddle about with bread/protoboards this weekend but I did find time to update my PCB and order a new revision. Lazy, I know.. but time is always short.

So this additional timing logic - is this something that's only required on modern EPROMs? Just curious since all of the Vic cartridge PCB's I've seen usually consist of nothing but a ROM and a capacitor. Are the newer EPROM (such as the AT28C256) a little bit quicker to assert the databus or something? Or is /OE provided by different means?

SparkyNZ wrote:So this additional timing logic [...]

/OE is used to prevent bus contention in case the (E)EPROM is selected via its /CS pin (here, because of the /BLK5 signal), but the CPU does a write. The inverted CR/W alone is not sufficient, in addition you also want the chip turn off its output drivers when the CPU is not 'on the bus' at all. This is the case for SΦ2=0. /OE = /(CR/W & SΦ2) does exactly that.

[...] is this something that's only required on modern EPROMs?

No. It's about good circuit design.

Just curious since all of the Vic cartridge PCB's I've seen usually consist of nothing but a ROM and a capacitor.

They were just cutting costs by all means and assumed either there were no 'writes' to the chip by design, or when they happened, could be tolerated. The latter is only the case for short times, and when both chips are TTL or NMOS. If at least one of the involved chips is CMOS, damage may result.

Mike wrote: ↑Sat Apr 05, 2025 6:47 am You really should use a 74LS00 and do /OE = /(CR/W & SΦ2) - as I already wrote, CR/W on its own has the wrong timing.

My v2 PCBs arrived today. Cartridge/ROM images started straight away. RAM bank switching also working. Happy chappy Now I'll have to get back to the reason I went down this path in the first place..