SparkyNZ,
you try to draw conclusions from the document that are not in any way backed by what is actually the case:
SparkyNZ wrote:So working with a PAL monitor, I guess the maximum display resolution for any (non-VIC) signal would be 704×576?
The TV norms as such do not define any horizontal resolution in pixels. When digitizing the signal from analog sources, there exist norms to which number of pixels a horizontal scan should be sampled for further processing and storage. This number of pixels in turn does not relate to the pixel rate of any computer video chip, the VIC-20 in particular.
71 cycles per line?
For PAL, yes.
So is that 3 VIC cycles to read char code, color code, pixel row?
The colour RAM is read in parallel to the text RAM, which is evident from the schematics. Thus a character is 2 CPU cycles wide on the VIC-20.
71/3 -> 23 char width max?
No. As I wrote above, this is a number following from false assumptions.
I guess the cycles per line varies depending upon the actual (white) screen width?
No. The number of cycles
used for video DMA per raster varies with the screen width, the total number of cycles remains at 71 (for PAL).
So is the (PAL) VIC generating 704 pixels of cyan per line before the lines are reached containing the white screen area? That 229 screen width is confusing me too - that would be a screen of 28 chars.. but then the screen width setting can be "0-29 makes sense, >32 will be interpreted as 32."
Oversized values in the register will lead to parts of the line being cropped horizontally for display, already on output of the VIC. Nonetheless, the offset to the next line will be honoured.
In short, you are grossly underestimating the necessary effort to create a FPGA replica of VIC-I. For what matters, there is a current project where Jon Brawn is working to exactly that goal, maybe it is a good idea you first read the corresponding threads here in Denial to get a grasp of it, "
6560 FPGA Progress." and "
FPGA 6561 - PAL Questions" in particular.
Greetings,
Michael