Denial

As cold weather coming up here, I intend to complete this little project..

There are many ram/rom expansions out in the wild, but most of them suffer from two problems ( IMO ). First, it use the expansion port, so without a port expander, your port is 'dedicate' to it. Secondly, it use dip switches to choose the amount of ram or rom slot to use( multi kernal ). For the internal expansion I saw, you have to open the 'hood' and move the dip switches.

So I come up with this board that I designed. Version 3 is coming up to fix the final hardware bugs. No solderingrequired ( if the cpu and the kernal are socketed )

The CPLD code need some work, as well as the microcontroller ( hidden under the 6502 )

The flash is 128k divided in 2 banks of 64k, subdivided in 8k slots. Why 2x64k ? Because one 64k will contain PAL ROM and the other one, NTSC. The first 4, 8k slots are reserved ( one is invisible ) for the VMMX, Kernal and Basic. Four free slots can be used, to put a diagrom, Jiffydos etc..

There's a 128k SRAM ( also hidden under the 6502 ). The first 64k is used for the RAM expansion, and the second 64k block, as 8k banked memory blocks.

The VMMX menu is coded in ASM without any kernal routine used. You can jump to the menu with a two keys combo from the Basic. You cannot jump in the menu if the kernal is not 'in use'.

More details about the banking and operation will come when it will be fully operational..

If there's any idea of feature to add, feel free to send them, it's an ongoing project so nothing is final.

Amazing work... This looks great.

Any idea as to how much $$$ this will be?

mythic66 wrote:No welding required [...]

Actually, I'd hope so.

BTW, that's an interesting date code (1837) on that "MOS" 65?02 CPU. :}

The world has gone mad on chip prices.

mingle wrote: ↑Mon Nov 13, 2023 3:22 am Amazing work... This looks great.

Any idea as to how much $$$ this will be?

thanks, no price yet, but it will be the bare minimum as I'm doing this as an hobby.

Mike wrote: ↑Mon Nov 13, 2023 1:58 pm

mythic66 wrote:No welding required [...]

Actually, I'd hope so.

BTW, that's an interesting date code (1837) on that "MOS" 65?02 CPU. :}

Yes, of course. I had to use SMD parts because I wanted to have the smallest footprint inside the vic20, so a 4 layers pcb
was also needed.

About the strange cpu date code, it's a batch I bought on Aliexpress, to avoid messing the 'real' 6502' in case of a failure, so
as you can see they are quite old 18th week of 1937

Rich wrote: ↑Mon Nov 13, 2023 2:06 pm The world has gone mad on chip prices.

I agree, but beside the cpld, the remaining chips are quite cheap.

mythic66 wrote:No welding required [...]

Mike wrote:Actually, I'd hope so.

mythic66 wrote:Yes, of course. I had to use SMD parts because I wanted to have the smallest footprint inside the vic20, so a 4 layers pcb was also needed.

As I think the pun got lost on that one - there's a clear distinction between soldering and welding. Soldering is a connection method that uses low-melting materials (the solder) to connect two (usually metallic) parts but those parts can also be disconnected by heating the joint once again without a permanent change in the structure of the two parts. In contrast, welding uses much higher temperatures and involves melting up the facing sides of the two parts at least to a degree. A welded joint cannot be disconnected without at least partly destroying the two welded parts.

In short - I wouldn't want to 'weld' anything inside my VIC-20, or on a PCB in general.

Mike wrote:BTW, that's an interesting date code (1837) on that "MOS" 65?02 CPU. :}

mythic66 wrote:About the strange cpu date code, it's a batch I bought on Aliexpress, [...]

Well, I did not expect otherwise. You most probably have a relabeled 65C02 here.

Mike wrote: ↑Tue Nov 14, 2023 6:31 am

mythic66 wrote:No welding required [...]

Mike wrote:Actually, I'd hope so.

mythic66 wrote:Yes, of course. I had to use SMD parts because I wanted to have the smallest footprint inside the vic20, so a 4 layers pcb was also needed.

As I think the pun got lost on that one - there's a clear distinction between soldering and welding. Soldering is a connection method that uses low-melting materials (the solder) to connect two (usually metallic) parts but those parts can also be disconnected by heating the joint once again without a permanent change in the structure of the two parts. In contrast, welding uses much higher temperatures and involves melting up the facing sides of the two parts at least to a degree. A welded joint cannot be disconnected without at least partly destroying the two welded parts.

In short - I wouldn't want to 'weld' anything inside my VIC-20, or on a PCB in general.

Mike wrote:BTW, that's an interesting date code (1837) on that "MOS" 65?02 CPU. :}

mythic66 wrote:About the strange cpu date code, it's a batch I bought on Aliexpress, [...]

Well, I did not expect otherwise. You most probably have a relabeled 65C02 here.

I agree, that soldering is more accurate than welding, I should have know, I'm a professional welder. English is not my first language, so mistakes here and there can slip in.

I had a question about memory banking. I want to keep it simple and not have a zillion of choices. Would it be better
to map 8k x 8 banks to a specified address BLK, or having 16k x 4 banks across 2 consecutives address BLK ( i.e BLK1-BLK2 )?

Any idea would be appreciated.

About the development, all the memory expansions as been completed and tested. I added the Write protect function for the BLK5.
I also added a CPU reset with the combining of the C= and left arrow.

mythic66 wrote:Would it be better to map 8k x 8 banks to a specified address BLK, or having 16k x 4 banks across 2 consecutives address BLK (i.e BLK1-BLK2)?

Being able to map any of the 8 KB blocks in your (assumed) total of 64 KB SRAM to any of the BLKx areas would be my preferred choice, hands down.

I also think you would quickly regret that inflexibility you'd incur with any assumptions about consecutive BLKs (i.e. your second proposal).

So being able to map, let's say two extra 8k blocks to BLK1, and four 8k blocks to BLK2 could be a case ? I'm trying to figure out real world application and how to implement this in the CPLD with the remaining resources.

The programmer would possibly want to store the data of 5 big game levels in, say, BLK3 and keep the assignments to BLK1, BLK2 and BLK5 constant.

Jim Brain and I had discussed this topic in deep when he developed Ultimem and he truly went for maximum flexibility here. Each one of the BLK address ranges, RAMx, I/O2 and I/O3 can be mapped to any 8K area of either cartridge RAM or Flash-ROM, be write-protected in case of RAM, or not be mapped at all.

On the other end of the spectrum we have the "Super-RAM" mode of FE3. There, the 512K cartridge RAM can only be switched in whole 32K steps, which in hindsight proved very inflexible. It took years for someone to come to terms with it enough to at least write a RAM disk for it.

Thanks Mike for the inputs, I'm gonna go read the topic with Jim to see how it goes. I wanted to keep the banking sample to avoid too much possibility and void compatibility problem but, if the programmer can control the banking behind the curtain as he want, this may do the trick.

Also, the bank switching is not done by using the IO addresses but by "poking" the value in the BASIC address range. BASIC is a read only so no chance to mess something, and as my board is directly on the CPU bus, I can scoop the write command to the BASIC range.

The UltiMem is really the One And Only for the VIC so far and as far as I know no-one really utilized it yet – for just launching files from ROM its features are overkill.