Actually, the 65xx features a state transition table to sequence the actions taken by each instruction cycle, not microcode.Groovydrifter wrote:that they triggered the execution of the following token in the microcode table of the processor.
As you explain some illegal opcodes have an almost equivalent documented one... but returning to the explanation on the article, this corresponds to a partial execution of the instruction microcode[...]
This is not a matter of tomatos/tomatoes; there is no microcode instruction counter in the 65xx. The STT features (just) 21 input lines, and 138 output lines. The undocumented instructions just happen to trigger combined actions of certain instructions, which would otherwise go separate, as intended.
In case of AAX, STA and STX are executed simultaneously, which results in an wired-AND inside the CPU: as soon as one bit of either A or X is 0, a 0 is also put on the data bus.
The screen displacement is understandable (the correct register init values are different for NTSC and PAL VICs), but would you care to tell me why the IEC bus is not supposed to work? I don't know of any differences in the IEC routines between NTSC and PAL.I already verified that NTSC kernals boot a PAL board with displaced image and not working IEC port.
Only the RS232 routines happen to use different tables for the baud rates, and the register init value for the jiffy clock is also different, in both cases because of 1.10 MHz (PAL) vs. 1.03 MHz (NTSC). And the jiffy clock runs with 60 Hz on both systems.
