Frustratingly slow progress, just not had the time to spend on this project much.
The SD2IEC is now all assembled and tested. I've used the wrong footprint for the RTC so it's patched up. It also survived me soldering it in upside down
The next task is to solder the PLCC sockets, I'm not looking forward to these.
Rather a long interval since the last post. Christmas happened, followed by vacation. I've spent far too much time on the hot plate (which still isn't complete). However, progress has been made.
The SMD PLCC sockets were difficult to hand solder. I again got too much paste under one and had to remove it. The plan for the future is to get some stencils so an even layer can be applied.
More mistakes were made. I had wired the data lines of the CPLD incorrectly in the schematic. I've patched up this board and I'm still re-routing for the next iteration of the PCB. I also chose a flash chip that was pin-compatible but didn't use the AMD programming sequence.
Just the label for the case to be ordered, then the next (final?) prototype to assemble.
Progress update: I've now got the next iteration of the PCB (with fixes). I switched the fabricator, I've got gold fingers plus chamfered edge for very little extra.
I have experimented with using a stencil to apply solder paste for the SMD sockets. It took a little while to get the stencil aligned but the result looks perfect.
I've seen glitches with the original board, I'm not sure if that's an artifact of some of the patching etc or whether it's cross-talk because of the way I've routed tracks. I'll retest on this new board once it's complete.
srowe wrote: ↑Sun Apr 06, 2025 12:19 pm
Progress update: I've now got the next iteration of the PCB (with fixes). I switched the fabricator, I've got gold fingers plus chamfered edge for very little extra.
I have experimented with using a stencil to apply solder paste for the SMD sockets. It took a little while to get the stencil aligned but the result looks perfect.
I've seen glitches with the original board, I'm not sure if that's an artifact of some of the patching etc or whether it's cross-talk because of the way I've routed tracks. I'll retest on this new board once it's complete.
Can't rush perfection; thanks for doing this, and for the update! -OGM
srowe wrote: ↑Sat Sep 28, 2024 2:59 am
Sure, what do you feel isn't covered well in the current User Guide?
I found the programming section hard to understand although it should be quite simple. But this one I couldn't take to the pub and be done with it before the second pint.
I've started writing a completely new document to explain the FE3 architecture. It's unfinished but hopefully it contains the sort of information you were looking for
It's entirely derived from my study of the schematic and the firmware, and writing a quantity of code that behaves as I expect. I wasn't involved in the original design & implementation so I'd appreciate feedback from anyone that was.
srowe wrote: ↑Fri Apr 18, 2025 1:57 am
[...]
I've started writing a completely new document to explain the FE3 architecture. It's unfinished but hopefully it contains the sort of information you were looking for
I've started writing a completely new document to explain the FE3 architecture. It's unfinished but hopefully it contains the sort of information you were looking for
It's entirely derived from my study of the schematic and the firmware, and writing a quantity of code that behaves as I expect. I wasn't involved in the original design & implementation so I'd appreciate feedback from anyone that was.
This is excellent! I too have been baffled concerning how the FE3 is programmed. I already am beginning to understand more of it from your draft document. Thank you for your work on this!
I've completed an initial version of the Programmers Guide and updated the PDF in the link above. I'd really appreciate any feedback on how to improve it or to correct any mistakes.