VIC-20CR, UF8, Databus buffer
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- mythic66
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VIC-20CR, UF8, Databus buffer
According to the schematic, UF8 purpose is to create a buffered databus to split CDB with BDB.
Doing some testing, i removed UF8 and bridged CDB(0-7) to BDB(0-7) and everything seems to work correctly. I tested
the penutimate and other apps and games, without any issues, so far.
Now the question is, what problems can occur while running with an UF8 bridged ?
Doing some testing, i removed UF8 and bridged CDB(0-7) to BDB(0-7) and everything seems to work correctly. I tested
the penutimate and other apps and games, without any issues, so far.
Now the question is, what problems can occur while running with an UF8 bridged ?
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Re: VIC-20CR, UF8, Databus buffer
This is only a guess on may part, but I think it would depend on what the CPU is being asked to do at the time with regards to the buses based on what the Datasheet states. There does appear to be some risk.
Joe
Joe
- Orangeman96
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- mythic66
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Re: VIC-20CR, UF8, Databus buffer
I'm trying to find out the pertinence of this comment toward the original question...Personally speaking, I would be hesitant to have that question "answered." -OGM
I didn't, out of the blue, come up with this idea. I replaced most of the glue logic chips with a CPLD
and I was running out of I/O, so I decided to give it a try.
- Orangeman96
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Re: VIC-20CR, UF8, Databus buffer
I have no idea what you're doing (lack of knowledge on my part), but it looks cool.
What prompted you to venture in this direction (just curious)?
Joe
What prompted you to venture in this direction (just curious)?
Joe
- mythic66
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Re: VIC-20CR, UF8, Databus buffer
Working on a project of a new VIC20 motherboard.. I'm still far from completion. I'm doing all separated section
that I will "glue" together.
that I will "glue" together.

- JonBrawn
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Re: VIC-20CR, UF8, Databus buffer
Are you planning on using modern 6502 devices, or vintage processors?
Working on FPGA replacement for 6560/6561
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Re: VIC-20CR, UF8, Databus buffer
Wow! That's sounds fun, exciting, and challenging.
Best of luck!
Joe
Best of luck!
Joe
- JonBrawn
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Re: VIC-20CR, UF8, Databus buffer
Back to the original question, what will happen if you install a RAM or ROM cartridge? I've not stared at the schematics enough with your question in mind yet, as I have my own hardware woes at the moment, but it's something worth looking at.
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- mythic66
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Re: VIC-20CR, UF8, Databus buffer
I used the penultimate cartridge , with different memory expansion, and games that was on the cartridge without an issue. I can't
believe that this 245 is there for nothing.
- JonBrawn
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Re: VIC-20CR, UF8, Databus buffer
The enable to the buffer is such that it can only be enabled when no external ROMs, RAM expanders (RAM1, RAM2, RAM3, BLK1, BLK2, BLK3, BLK5), IO2 or IO3 devices, the BASIC ROM (BLK6) or the KERNAL ROM (BLK7) are enabled. That's done by that many input NAND gate, UD9. All of these active low device select signals have to be inactive before the output can go low to enable the buffer.
ALSO the system phase 2 clock needs to be high, which is the phase during which the 6502 has control of the data and address busses, so it's isolating the VIC databus from the CPU data bus unless the CPU is in charge, which will prevent the VIC from reading from devices that are connected to the CPU data bus, such as the expansion slot and the BASIC and KERNAL ROMs.
There's obviously some clever reason why they want to isolate the VIC from so much - but given that the VIC's address range is limited to $0000-$1FFF and $8000-$9FFF I'm not sure why this would be important. Maybe it violates timing so badly it'll upset the external devices?
Does this seem like a reasonable interpretation of the schematics?
You might be able to confirm (or deny) this by adding a 3K RAM expansion to the expansion port and seeing if you can put video or character data there and get it displayed. With an unmodified VIC-20 it won't work.
ALSO the system phase 2 clock needs to be high, which is the phase during which the 6502 has control of the data and address busses, so it's isolating the VIC databus from the CPU data bus unless the CPU is in charge, which will prevent the VIC from reading from devices that are connected to the CPU data bus, such as the expansion slot and the BASIC and KERNAL ROMs.
There's obviously some clever reason why they want to isolate the VIC from so much - but given that the VIC's address range is limited to $0000-$1FFF and $8000-$9FFF I'm not sure why this would be important. Maybe it violates timing so badly it'll upset the external devices?
Does this seem like a reasonable interpretation of the schematics?
You might be able to confirm (or deny) this by adding a 3K RAM expansion to the expansion port and seeing if you can put video or character data there and get it displayed. With an unmodified VIC-20 it won't work.
Working on FPGA replacement for 6560/6561
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- Mike
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Re: VIC-20CR, UF8, Databus buffer
That also won't work with UF8 removed. Even though VIC-I now has its data lines connected to the cartridge data bus, its address lines still 'end' at the other (address bus) buffers which are fixed to the CA -> VA direction. The /RAMx signals get activated though, but VIC will fetch essential random data (the lower address bits being supplied by the CPU address bus instead).JonBrawn wrote:You might be able to confirm (or deny) this by adding a 3K RAM expansion to the expansion port and seeing if you can put video or character data there and get it displayed. With an unmodified VIC-20 it won't work.
IMO, UF8 is supposed to isolate CDx and BDx so the CPU only has to drive either side of the data bus, and all the internal RAM chips and the character ROM also only need to drive the VIC side of the data bus. The VIC-I chip needs fast response from memory for graphics data, and - with UF8 removed - I expect the video quality to worsen significantly ('snow' and other glitches), if more than one cartridge is used with an unbuffered cartridge extender. Good quality cartridge extenders likewise feature a set of three '245 buffers to drive the extended bus.