The "VIC-2000000"

[brain]

The "VIC-2Million"



I know, it looks pretty simplistic.

2MB of SRAM (under the PCB), 512kB of FLASH, sits in the CPU socket, nothing special.

But, since it's hard to use all that RAM with an '02, the unit has an on board 65C816S, which you can select to use under software control

I'm planning to set it up and maybe do some development at the Vintage Computer Festival Midwest this weekend.

Yep, the plan is to run the '816 faster than 1MHz, but projects have to crawl, walk, and then run. I'm just glad I was able to isolate the NMOS 6502 from the VIC-20 circuitry and enable the '816.

[eslapion]

@Brain
I see just like me you have a fondness for Xilinx's XC95 series of CPLD.

Any reason why you're not using the WDC version of the 65816 ?

[brain]

Didn't have one in my parts box. Wasn't planning to get this far along at this point in the project, as I was assuming it would take weeks just to get the 6502 to behave in the new circuit. But, I'll fix it soon enough. Ordering 3 of the WDC units from Mouser tomorrow.

[sjgray]

Very cool!

Steve

[joshuadenmark]

I am impressed, wow

[majikeyric]

Very promising SuperVIC !

[brain]

Well, since VCF-MW is over, been playing around with the functionality, concentrating on memory right now.

I have now broken the memory partitioning into 8 8kB chunks, which can be enabled or disabled at will

I have also tested mapping the RAM under the KERNAL, mirroring it, and then swapping out the KERNAL ROM. That is cool.

CPU swapping does not like the RAM being swapped into KERNAL right now, so I am checking on why that occurs, but I assume it's a trivial item.

Thus, with this mod, even without the CPU addition, you could approximate the C64 memory mapping...

Jim

[eslapion]

@brain
If you can "shadowram" the kernal then you could easily modify it, once in RAM, for proper functioning at higher CPU speeds.

[brain]

@brain
If you can "shadowram" the kernal then you could easily modify it, once in RAM, for proper functioning at higher CPU speeds.

That is the plan.

JIm

[Kakemoms]

Didn't have one in my parts box. Wasn't planning to get this far along at this point in the project, as I was assuming it would take weeks just to get the 6502 to behave in the new circuit. But, I'll fix it soon enough. Ordering 3 of the WDC units from Mouser tomorrow.

I like the way you use PLD to get things smaller. I haven't used them but I need to start looking into that. 74xxx logic is kind of nice, but one gets tired of soldering and resoldering in the long run.. Someone at 6502.org wanted me to start wire-wrapping instead and I can see the point in that now.

[eslapion]

I like the way you use PLA to get things smaller.

???

What PLA ?

[Kakemoms]

I like the way you use PLA to get things smaller.

???

What PLA ?

Typo. PLD or CPLD. But that was obvious for all other people here eslapion.

This guy put the whole 6502 into a CPLD, in which case you could drop the external CPUs.

[eslapion]

Typo. PLD or CPLD. But that was obvious for all other people here eslapion.

That's me and my life through a piece of straw...

This guy put the whole 6502 into a CPLD, in which case you could drop the external CPUs.

Gideon Zweijtzer did the same on the 1541 U/U2 but this specific project is interesting because it only took him 72 macrocells to achieve it.

Of course the result is this 6502 doesn't support illegal opcodes, the same as a standard CMOS 6502. Also, this is a 6502 which communicates through SPI so it's not about to be used in a VIC-20 accelerator.

[brain]

Not to discount the great work in the 65SPI space, but it's not a 6502.

It's simply an SPI to parallel interface, like a 6522 does synchronous serial.

Not that it provides a good rule of thumb, but each bit of storage in a system will require 1 macrocell. So, the 6502, which requires 16 PC+ 8 SR + 8 X + 8 Y + 8 A + 8 ST requires at least 56 macrocells.

It's a useless metric for CPUs, since the ALU will take macrocells, and the "ROM" microcode also takes up macrocells, but it can give a lower bound on size. For instance, the REU is pretty simple, but has 16 bits for 64 address, 18-20 bits for REU address, a 16 bit counter and a 16 bit length register, as I recall. Thus, it will require at minimum a CPLD with 66-68 macrocells to implement, which means a 9572 is a poor choice, and a 144 might not be large enough.

Jim

[eslapion]

Not to discount the great work in the 65SPI space, but it's not a 6502.

It's simply an SPI to parallel interface, like a 6522 does synchronous serial.

Makes more sense. This is a 6502 bus to SPI interfacing chip.