VICMem

[brain]

Dragos (of IEEE 488 replica fame), asked if I could whip up a small design for those wanting to roll their own cartridges. I sent him back this:



Very simple. Install bottom 2 ICs for ROM use, top two for RAM, All for combo. jumper selects which BLK signals access ROM or RAM. Nothing special, but maybe helpful.

Jim

[eslapion]

On the Ultimate Expander (2006), I used a footprint that could accomodate a surface mount or wide DIP or skinny DIP 32k x 8 SRAM chip.

Your board can only accomodate the skinny DIP type which in fact I turned out never to have used. These are usually very fast SRAM that were used as cache on older 486/Pentium I PC motherboards and have a reaction type of 15-20ns. They don't behave very well on a VIC which signals at a much slower speed.

Keys' Mini 32k SRAM board uses a wide DIP Cypress 32k x 8 SRAM chip which is much better suited than any skinny DIP SRAM.

[brain]

I will add a wide DIP footprint, but the cheapest 32kB SRAM is the skinny DIP, at least for new purchases in the US.

http://www.digikey.com/product-search/e ... geSize=500

[dragos]

well, I'll let you know how the skinny dip version works because my proto order is already submitted...

[eslapion]

I will add a wide DIP footprint, but the cheapest 32kB SRAM is the skinny DIP, at least for new purchases in the US.

http://www.digikey.com/product-search/e ... geSize=500

All the 55ns and 70ns chips in the list you provided are 0.6" wide. The only 0.3" chip is the one you should avoid... 15ns and the difference in price is 13 cents.

Anyways, this is even cheaper:
http://www.ebay.ca/itm/SRAM-32kx8-Stati ... 3cf8f1636b

If you absolutely want a new chip, IMHO, this is a much more relevant search and, as you can see, SOIC chips are the cheapest and they do have adequate response speeds:
http://www.digikey.com/product-search/e ... geSize=500

[brain]

Why should we stay away from 15nS SRAMs?

I understand eBay is a great source of products, but the original request was for a repeatable offering, and so I use digikey for the sourcing.

I did not pursue SOIC/TSOP/SOP because Dragos said he could only handle through hole.

Jim

[eslapion]

Why should we stay away from 15nS SRAMs?

When looking at the chatter these very fast chips cause on the bus of a slow machine like a VIC, 64 or any older 8 bit 1-2MHz machines, these chips interpret the slow transitions of the digital signaling they receive as incertitude for a brief period of time. The Mach210 used on the SuperPLA V3 (Jens Schönfeld) has the same problem.

This causes high frequency noise on the databus as well as on the 5V/GND lines especially during the few ns when they can't clearly decide if the !CS or !OE is high or low. This happens almost everytime they are accessed.

By their very nature, fast memory chips, RAM or ROM, cause power spikes when selected. To add to that, in a VIC or 64, they toggle on and off a bunch of times almost everytime they are accessed.

I did not pursue SOIC/TSOP/SOP because Dragos said he could only handle through hole.

I only used the lower pin density SOIC myself on the Ultimate expanders but if through-hole is an absolute requirement then i strongly suggest you go with the wider 0.6" DIP ICs because they consistently carry slower memory chips that react adequality to slow transition signal and they have a greater output (signaling) impedance which prevents the above mentioned noise on the databus and on the Vcc/GND.

As I said, even your own research link shows these chips are only a few pennies more expensive.

As for eBay, for the last 9 years, I was always able to find a source or another of various types of 32k x 8 parallel jedec compliant SRAM chips from a wide variety of manufacturers and at a price consistently lower than new chips.

[brain]

When looking at the chatter these very fast chips cause on the bus of a slow machine like a VIC, 64 or any older 8 bit 1-2MHz machines, these chips interpret the slow transitions of the digital signaling they receive as incertitude for a brief period of time. The Mach210 used on the SuperPLA V3 (Jens Schönfeld) has the same problem.

I understand the chatter in a PLA-like situation, but in this case, RAM is only going to be accessed if one of the BLK signals, which are gated via CLK and go through a LS-speed TTL decoder. In my tests, there's been little to no chatter on the BLK signals. The address lines chatter, but not the gated BLK lines

As I said, even your own research link shows these chips are only a few pennies more expensive.

Yes, they are, but I design for every penny of savings, as I know folks care about those things.

That said, it was trivial to add a .6" footprint, and though I do not agree with your position on fast SRAM per se, I do agree a larger footprint gives folks more options, which is important in this design.

As for eBay, for the last 9 years, I was always able to find a source or another of various types of 32k x 8 parallel jedec compliant SRAM chips from a wide variety of manufacturers and at a price consistently lower than new chips.

Again, I understand, but I don't design that way. I design for new part options, and then I may check to see if eBay can provide a supply.

Jim

[eslapion]

I understand the chatter in a PLA-like situation, but in this case, RAM is only going to be accessed if one of the BLK signals, which are gated via CLK and go through a LS-speed TTL decoder. In my tests, there's been little to no chatter on the BLK signals. The address lines chatter, but not the gated BLK lines

I truly don't understand the relevance of your comparison with a PLA situation. In the VIC, glue-logic LS series chips perform the same function. There is no such thing as a CASRAM required delay in the VIC since it uses no DRAM but otherwise its exactly the same thing.

The chatter I am referring to is the spikes caused on the power lines when low impedance output chips start signaling and the 5V line is much more sensitive on the VIC than on the 64 which has larger and more numerous capacitors to protect it. It has nothing to do with the BLK signals or adress bus.

The VIC's internal power architecture was not designed to handle the brutal power load variations caused by the activation/deactivation of very fast RAM or ROM chips. Since these specific cache SRAM chips toggle very quickly and erratically between on and off when the BLK lines goes low at a relatively slow rate, this causes a bunch of ripples on the Vcc inside the whole machine everytime you access them. This can cause reliability problems with every circuit inside the VIC-20. It can also damage the 5V linear regulator used in the 2 Prong VICs.

Yes, they are, but I design for every penny of savings, as I know folks care about those things.

IMHO, in this specific case a few pennies saved can represent a ton of trouble.

For example, on the C64 even the TurboMaster which uses a pair of 32k x 8 SRAM chips is fitted with slow/wide chips because the designer realised cheaper PC cache SRAM chips caused spikes on the 5V and ground lines (ground bouncing) and this caused all sorts of random technical issues.

That said, it was trivial to add a .6" footprint, and though I do not agree with your position on fast SRAM per se, I do agree a larger footprint gives folks more options, which is important in this design.

If its trivial to do the right thing, then why not do it?

[brain]

I truly don't understand the relevance of your comparison with a PLA situation.

I referenced the PLA as you had done so in an earlier comment:

The Mach210 used on the SuperPLA V3 (Jens Schönfeld) has the same problem.

The chatter I am referring to is the spikes caused on the power lines when low impedance output chips start signaling and the 5V line is much more sensitive on the VIC than on the 64 which has larger and more numerous capacitors to protect it. It has nothing to do with the BLK signals or adress bus.

I understand your position, and it is a concern with some IC families and use cases, but it is not a universal truth.

The VIC's internal power architecture was not designed to handle the brutal power load variations caused by the activation/deactivation of very fast RAM or ROM chips. Since these specific cache SRAM chips toggle very quickly and erratically between on and off when the BLK lines goes low at a relatively slow rate, this causes a bunch of ripples on the Vcc inside the whole machine everytime you access them. This can cause reliability problems with every circuit inside the VIC-20. It can also damage the 5V linear regulator used in the 2 Prong VICs.

In my testing, I am not witnessing the issue you are describing. I see a clean transition on BLK5 going low, and a smooth orderly transition of the SRAM data lines. When testing the power rail, I do not see spikes or droops in output. Yes, if BLK5 behaved erratically, I would agree the issue would manifest itself and thus BLK5 should be gated with PHI, but I have not found that to be the case.

IMHO, in this specific case a few pennies saved can represent a ton of trouble.

I appreciate the concern, and I take time to ensure my designs are both economical and safe.

For example, on the C64 even the TurboMaster which uses a pair of 32k x 8 SRAM chips is fitted with slow/wide chips because the designer realised cheaper PC cache SRAM chips caused spikes on the 5V and ground lines (ground bouncing) and this caused all sorts of random technical issues.

I have not studied the TM design in depth, but there are many ways to address this issue besides moving to slower SRAM. If the designer opted for slower SRAM, I assume the solution was the least expensive to implement.

If its trivial to do the right thing, then why not do it?

I respectfully disagree with your power analysis, but I do agree that offering more choices (as someone may find a nice stash of .6" SRAMs in their parts box or on eBay) is a fine suggestion.

[eslapion]

I truly don't understand the relevance of your comparison with a PLA situation.

I referenced the PLA as you had done so in an earlier comment:

The Mach210 used on the SuperPLA V3 (Jens Schönfeld) has the same problem.

Yeah, the Mach210 doesn't know what foot to dance on when its fed a slow transistion signal. Its really designed for fast digital signals but that's not specific to its usage as a PLA. Nonetheless, its why the SuperPLA V3, which is based on that chip is not compatible with FastLoad.

The chatter I am referring to is the spikes caused on the power lines when low impedance output chips start signaling and the 5V line is much more sensitive on the VIC than on the 64 which has larger and more numerous capacitors to protect it. It has nothing to do with the BLK signals or adress bus.

I understand your position, and it is a concern with some IC families and use cases, but it is not a universal truth.

I agree, please see below.

The VIC's internal power architecture was not designed to handle the brutal power load variations caused by the activation/deactivation of very fast RAM or ROM chips. Since these specific cache SRAM chips toggle very quickly and erratically between on and off when the BLK lines goes low at a relatively slow rate, this causes a bunch of ripples on the Vcc inside the whole machine everytime you access them. This can cause reliability problems with every circuit inside the VIC-20. It can also damage the 5V linear regulator used in the 2 Prong VICs.

In my testing, I am not witnessing the issue you are describing. I see a clean transition on BLK5 going low, and a smooth orderly transition of the SRAM data lines. When testing the power rail, I do not see spikes or droops in output. Yes, if BLK5 behaved erratically, I would agree the issue would manifest itself and thus BLK5 should be gated with PHI, but I have not found that to be the case.

As I said above, this has nothing to do with the BLK signals. It has everything to do with how your SRAM chip understands it.

No two SRAM chips, even those rated for 20ns or less, will have exactly the same behavior. Maybe you were just lucky. I would be tempeted to say the problem is more likely to occur if you have a multicart expander as this increases the resistive and capacitive load on the BLK lines and therefore lowers the slew rate.

Some chip will exhibit this problem badly, some won't do it at all because they have hysteresis on all inputs including the !CE or !OE. IMHO, the Winbond cache SRAMs which were used a lot in cheap 386/486 PCs are about the worst.

I admit I have little experience with fast SRAM chips that are still in production and its even possible improvements have been implemented to avoid this erratic behavior in all of them.

[brain]

As I said above, this has nothing to do with the BLK signals. It has everything to do with how your SRAM chip understands it.

You should read my original comment as "BLK5's transition to low's affect on the SRAM behavior". If BLK5's transition was glitchy or erratic, which could occur if the '138 that drives BLK5 was not gated with PHI, then the SRAM would behave erratically, as it would see what looks like multiple requests for data reads. But, I do not see that on the scope or the LA.

No two SRAM chips, even those rated for 20ns or less, will have exactly the same behavior. Maybe you were just lucky.

I am confident that the SRAMs will be the same within a reasonable tolerance, as described in the datasheet. I agree they will not be exactly the same, but will be so within a statistical tolerance.

I would be tempeted to say the problem is more likely to occur if you have a multicart expander as this increases the resistive and capacitive load on the BLK lines and therefore lowers the slew rate.

Yes, but it is impossible to factor that in, because there were/are so many expander designs, and some are worse than others.

I admit I have little experience with fast SRAM chips that are still in production and its even possible improvements have been implemented to avoid this erratic behavior in all of them.

New parts will have slew rate control on the outputs, due to the issues you describe. Too fast a slew rate will exhibit ringing on data lines that do not have the exact impedence of the IC (as the data line is now acting as a transmission line, and transmission line theory governs). Nonetheless, choice of decoupling caps are important at the corner cases. As I look at the Sony (ebay.ca link) and Cypress parts' datasheets, both have 8nF capacitance on the outputs, and both appear to have similar slew rates.

Jim

[MCes]

Hi Brain,
but if I remember well the right signal to drive the /WRITE pin of the RAM is VRW (PIN 17 on cartridge connector) and not the CRW (PIN 18 on cartridge connector).

Is it relevant?

[dragos]

I got my prototypes in, just need to order parts now. I thought you would like to see them:

https://www.flickr.com/photos/92448698@ ... 264712786/

[eslapion]

I know I may seem persistent on this but a comment from Skoe made me realise a very fast SRAM chip could cause ringing on the databus.